Tag: hardware

Apple A13

Apple’s new chip contains 8.5b transistors. Also, there are 6 CPU cores: 2 high-performance cores running at 2.66 GHz, and 4 efficiency cores. It has a quad-core graphics processor, an LTE modem, an Apple-designed image processor, and an 8-core neural engine for machine intelligence functions that can run 1t operations per second.

This new chip is smarter, faster, and beefier, and yet it somehow manages to consume less power than its predecessor. It’s 30% more efficient than last year’s A12 chip, 1 of the factors that contributes to the extra 5 hours per day of battery life in the new iPhones.

Intel Secure Enclave Attack

Our SGX-ROP attack uses new TSX-based memory-disclosure primitive and a write-anything-anywhere primitive to construct a code-reuse attack from within an enclave which is then inadvertently executed by the host application. With SGX-ROP, we bypass ASLR, stack canaries, and address sanitizer. We demonstrate that instead of protecting users from harm, SGX currently poses a security threat, facilitating so-called super-malware with ready-to-hit exploits.

Bricked shoes

Nike users are experiencing some technical difficulties in the wild world of connected footwear. Nike’s $350 “Adapt BB” sneakers are the latest in the company’s line of self-lacing shoes, and they come with the “Nike Adapt” app for Android and iOS. The app pairs with the shoes and lets you adjust the tightness of the laces, customize the lights (yeah, there are lights), and see, uh, how much battery life your shoes have left. The only problem: Nike’s Android app doesn’t work.

330 TB memory

Combining these technologies, we were able to read and write data in our laboratory system at a linear density of 818K bits per inch. (For historical reasons, tape engineers around the world measure data density in inches.) In combination with the 246200 tracks per inch that the new technology can handle, our prototype unit achieved an areal density of 201 gigabits per square inch. Assuming that one cartridge can hold 1140 meters of tape—a reasonable assumption, based on the reduced thickness of the new tape media we used—this areal density corresponds to a cartridge capacity of a whopping 330 TB. That means that a single tape cartridge could record as much data as a wheelbarrow full of hard drives.

Easy robotics

if you’ve ever wanted to dabble in robotics or motion control, but have been daunted by control theory and arcane driver protocols (like I’ve been), check out the IQ Position Module. They are crowdfunding now at CrowdSupply. I backed their campaign to reserve a few more Position Modules for my lab – by wrapping a smart computer around a dumb motor, they’ve created a widget that lets me go from code to physical position and back with a minimal amount of wiring and an accessible API.

RISC-V

RISC-V is a open instruction set architecture originally developed at UC Berkeley for research and education that has been seeing a lot of exciting developments lately. You can buy a RISV-V based microcontroller right now. It is officially supported by GCC. The lowRISC project, founded by some of the same people responsible for Raspberry Pi, aims to provide a fully open source Linux system-on-a-chip. UC Berkeley has developed a (relatively) high performance, super-scalar, out-of-order RISC-V core.

2023-02-11: RISC-V status update. I remain skeptical because only losing players have adopted it, probably out of a position of weakness. Citing government investments as helpful is hilarious.

RISC-V is inevitable. RISC-V is going to have the best processors. And RISC-V is going to have the best ecosystem. All the technical stuff in RISC-V is amazing, but it’s really this change in the business model that makes RISC-V inevitable. And just think about this: Once you move to a high-quality open standard, you never go back to sole-source proprietary standards.

Mythic

Mythic can do an 8-bit multiply and add in a single transistor

2020-10-17: AI Analog Compute

Mythic is the first and only company that have been able to implement a deep learning model like ResNet 50 in a non-digital architecture: > 50 layers, 1000 fps, 3W total, 9->2ms latency, 8 TOPS/W in 40nm silicon. 10x cost advantage over digital chips.

2023-04-11: Commercialization takes a long time

Mythic’s analog chip uses less power by storing neural weights not in SRAM but in flash memory, which doesn’t consume power to retain its state. And the flash memory is embedded in a processing chip, a configuration Mythic calls “compute-in-memory.” Instead of consuming a lot of power moving millions of bytes back and forth between memory and a CPU (as a digital computer does), some processing is done locally. Mythic’s success on that front has been variable: The company ran out of cash and raised $13 million in new funding and appointed a new CEO.
I asked him whether the state of analog computing today could be compared to that of quantum computing 25 years ago. Could it follow a similar path of development, from fringe consideration to common (and well-funded) acceptance?

It would take a fraction of the time. “We have our experimental results. It has proven itself. If there is a group that wants to make it user-friendly, within 1 year we could have it.” And at this point he is willing to provide analog computer boards to interested researchers, who can use them with Achour’s compiler.

Moore’s Law over 120 Years

I updated the Kurzweil version of Moore’s Law to include the latest data points. Further UPDATE here, post Tesla AI Day. Of all of the variations of Moore’s Law, this is the one I find to be most useful, as it captures what customers actually value — computation per $ spent. Humanity’s capacity to compute has compounded for as long as we can measure it, starting long before Intel co-founder Gordon Moore noticed a refraction of the longer-term trend in the belly of the then fledgling semiconductor industry. But, Intel has ceded leadership for Moore’s Law. The 7 most recent data points are all NVIDIA GPUs, with CPU architectures dominating the prior 30 years. The fine-grained parallel compute architecture of a GPU maps better to the needs of deep learning than a CPU. There is a poetic beauty to the computational similarity of a processor optimized for graphics processing and the computational needs of a sensory cortex, as commonly seen in neural networks today.